A 200–240-GHz Transmitter Front-End with 6-bit Phase Shifting in 130nm SiGe BiCMOS

This work presents a J-band transmitter front-end with an integrated 6-bit vector modulator phase shifter (VMPS) and power amplifier in 130nm SiGe BiCMOS technology. Lange couplers and Marchand baluns are adopted to generate I/Q signal with better amplitude and phase balance. Phase inverter-embedded variable gain amplifiers are applied to gain control of I/Q signal, and the modulated I/Q signal is orthogonally added in the current domain through a highly compact T-shaped microstrip line. The combined differential signal from the phase shifter directly drives the connected two-stage cascode power amplifier, reducing connection loss between the phase shifter and amplifier. The front-end is post-simulated from 200 to 240 GHz with 7.5 dB average gain and 7.1 dBm average saturated output power while the RMS gain error remains less than 0.34 dB. The RMS phase error can achieve 1.23° at 232 GHz and remains below 2.5° from 205 to 240 GHz for 360° phase tuning range. The chip consumes a DC power of 245 mW and occupies a core area of only 0.18 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.

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Published
2024-08-21
DOI
https://doi.org/10.1109/ucmmt62975.2024.10737792
Citations
1
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.21

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article

A 200–240-GHz Transmitter Front-End with 6-bit Phase Shifting in 130nm SiGe BiCMOS

Peigen Zhou, Lingzheng Kong, Wei Hong, Zekun Li et al.
1 citations
Radio Frequency Integrated Circuit Design
0.21
article

A 200–240-GHz Transmitter Front-End with 6-bit Phase Shifting in 130nm SiGe BiCMOS

Peigen Zhou, Lingzheng Kong, Wei Hong, Zekun Li, Chang Shu, Jixin Chen
article en
1 citations

Abstract

This work presents a J-band transmitter front-end with an integrated 6-bit vector modulator phase shifter (VMPS) and power amplifier in 130nm SiGe BiCMOS technology. Lange couplers and Marchand baluns are adopted to generate I/Q signal with better amplitude and phase balance. Phase inverter-embedded variable gain amplifiers are applied to gain control of I/Q signal, and the modulated I/Q signal is orthogonally added in the current domain through a highly compact T-shaped microstrip line. The combined differential signal from the phase shifter directly drives the connected two-stage cascode power amplifier, reducing connection loss between the phase shifter and amplifier. The front-end is post-simulated from 200 to 240 GHz with 7.5 dB average gain and 7.1 dBm average saturated output power while the RMS gain error remains less than 0.34 dB. The RMS phase error can achieve 1.23° at 232 GHz and remains below 2.5° from 205 to 240 GHz for 360° phase tuning range. The chip consumes a DC power of 245 mW and occupies a core area of only 0.18 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.

State Key Laboratory of Millimeter Waves, Southeast University (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 46%
Radio Frequency Integrated Circuit Design
0.21
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