Front-End Designing and Implementation of Vedic Multiplier

This research introduces a novel approach to designing and implementing a high-speed Vedic multiplier utilizing the Urdhva Triyakbhyam Sutra. Employing Vivado 22.2 and Verilog as primary tools, our objective was to engineer a multiplier optimized for speed and efficiency. The initial phase commenced with the development of a 2×2 stage, which seamlessly scaled up to a 16×16 multiplier while maintaining consistent performance and scalability. Integration of partial product stages was facilitated through the utilization of Carry Look Ahead Adders (CLAs), enhancing overall efficiency. Through extensive comparative analysis, our multiplier demonstrated a notable reduction in delay and efficient resource utilization. Notably, it exhibited commendable power efficiency, showcasing its suitability for diverse applications. This implementation marks a significant stride in the realm of arithmetic computation, underscoring our commitment to advancing computational capabilities.