Verilog based Architecture Computing Testability Measures for DFT Designers

Testability measures of any circuit quantifies the difficulty level of put any value (0 or 1) on a particular signal path of the circuit and observe the signal value effect at the output of the circuit termed as controllability and observability (CC&CO). Detectability provides a measure of any stuck at fault detection probability. The circuits designers must consider the testability measures and detectability to ensure the ease of testing. The proposed architecture allows the designer to analyze the selection of gates for implementation of various functionalities. Verilog HDL codes are written to measure CC&CO for all possible 216 designs based the proposed architecture. Simulation results indicate the variation of CC&CO for different combinations of gates. It has been observed that the designs having NAND/NOR gates only have the least value of CC&CO as well as highest detectability.