Automatic Gain Control on FPGA for Multi-Antenna GNSS Receivers

In this work an Automatic Gain Control (AGC) for Global Navigation Satellite System (GNSS) receivers with multiple antennas is presented. The implementation was done in an FPGA and it was integrated with the embedded system of the receiver digital processing stage. The implementation directly in hardware allows one to control all the channels in a simultaneous way, which is a basic requirement for some GNSS applications. The AGC module was coded in VHDL and it includes a bus interface to communicate with the receiver microprocessor. The AGC functioning is completely autonomous but this interface lets one monitor and change some algorithm parameters in real time. A custom SPI interface was also integrated with the AGC module in order to program the compatible Variable Gain Amplifiers (VGA). The validation process was done in two stages. In the first one, an open loop test was carried out using a simulated signal. In the second stage, a real GNSS receiver was used to do a closed loop validation with a synthetized signal. The open loop validation stage was useful to test the main configuration parameters of the implementation while the closed loop tests were used to validate the end-to-end AGC algorithm. The complexity analysis of the design showed a few logic resources required which helps the implementation in almost any modern FPGA.