An Optimized Low Power 10T SRAM using FinFET Technology

The purpose of this study is to create and investigate a low-power 10T Static Random-Access Memory (SRAM) cell that is optimised for usage with Fin Field-Effect Transistor (FinFET) technology. The first step in the research process involves the development of a 10T SRAM model by leveraging Metal-Oxide- Semiconductor Field- Effect Transistor (MOSFET) technology as a baseline. The HSPICE tool is utilised to gain first insights into the performance of the model. Investigating the benefits of FinFET technology in terms of boosting power efficiency, decreasing latency, and enhancing the power-delay-product (PDP) in SRAM cells is the primary purpose of this study. The research is being carried out in the 16nm technological node, and it makes use of SPICE code simulations in order to thoroughly analyse and compare the characteristics of FinFET-based circuits to those of their MOSFET counterparts, particularly in low-power applications. The Average Power Consumption, Power Dissipation, Power Dissipation Progress (PDP), and Delay are all important performance measures. The objective of this study is to bring attention to the potential advantages of introducing FinFET technology into SRAM cell designs, with a particular emphasis on striking a balance between improved performance and power efficiency. It is anticipated that the outcomes will have a considerable impact on the advances that will take place in memory architectures in the future, which will present new prospects for the growth of SRAM technology.