Improving CPU Fault Injection Simulations: Insights from RTL to Instruction-Level Models

Fault injection simulators are essential tools for evaluating the robustness of software programs against hardware faults. Instruction-level simulators offer high speed but lack accuracy, whereas register-transfer level (RTL) simulators provide high accuracy but are slow. This paper demonstrates that the accuracy of instruction-level simulators can be significantly improved by modeling fault effects observed in RTL-level simulations and incorporating those models into the instruction-level simulator. The fault effect models are designed to capture only architecturally visible changes to the CPU state. We first introduce a model based on characterization on the probabilities of observed fault effects, which improves upon traditional models such as NOP and instruction bitflip. By observing how faults affect specific CPU registers, we improve this further and define the ‘regonly’ model. This model achieves significantly higher accuracy than the other models with respect to RTL-level simulations, without incurring the computational overhead associated with RTLbased simulations.