Moving Average Filter Block Implementation Using USP-Awadhoot Divider

In IoT systems, compact, battery-operated circuitry, and rapid data transmission are essential for reducing power consumption and extending battery life. Efficient data transmission requires robust local data processing capabilities supported by appropriate arithmetic and logical units (ALU). Modern processors or field-programmable gate arrays (FPGA) with a suitable ALU are well-suited for meeting these demands. To ensure data quality, effective signal processing before transmission is crucial. A moving average filter (MAF) is an excellent choice for this purpose, providing a balance of speed and precision while utilizing minimal hardware resources, thereby reducing the chip area needed for implementation. This article describes the design and implementation of the moving average low pass filter using the area-efficient novel USP-Awadhoot divider. The proposed USP-Awadhoot divider requires 266 LUTs and 146 FFs for 8-bit implementation using Xilinx FPGA. The proposed moving average filter based on a novel USP-Awadhoot divider is implemented on Nexys A7 XC7A100T-1CSG324C FPGA boards with Xilinx Vivado Design Suite. It is suitable for the cost-effective implementation of IoT and battery-operated applications.