Design of CMOS Voltage Reference Circuit using LDD MOSFETs in BCD 110nm Technology

This work presents a voltage reference that uses lightly doped drain MOSFETs to achieve a low area and low sensitivity. The circuit operates within the voltage range of 0.98V to 2V for the minimum supply voltage and maximum supply voltage. This circuit has a temperature coefficient of 61.02 ppm/°C. This circuit has a line sensitivity of 0.042%/V. The area of the chip is 0.000309 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The design has been simulated using Cadence Virtuoso and ELDO simulator tool for 110nm BCD technology and the layout of this circuit is completed using Cadence Virtuoso tool and Mentor Calibre for physical verifications.