A Novel Hybrid CMOS Full Adder with Low Power and High Speed for Embedded Systems

A low-power and high-speed CMOS (Complimentary Metal Oxide Semiconductor Logic) complete Full adder core is suggested for embedded systems in this work. This novel hybrid Full adder design consists of two different logic styles which is named as static CMOS logic and the pass-transistor logic, the present full adder digital circuit is based on a new three-input exclusive OR (3-XOR) design. Here in this novel full adder design the primary goal of this circuit is to provide the driving capability in addition it also gives the fast speed and low power consumption. The experimental circuit's properties, when compared to previous literature, demonstrate that the novel adder improves power consumption by 3.6% to 32.8%, time delay of Co by 10.9% to 40.6%, and power-delay product of Co by 12.9% to 90.9% by using the TSMC CMOS 0.35-µm technology which is also suitable for Mixed-Signal circuits. Out of all the Full adders which are chosen here for the comparison, the circuit has been shown to have the lowest consumption of power and there is a quickest carryout signal response. The new hybrid full adder and the XOR logic can be effectively integrated in an embedded system or SoC because of their high speed as well as where the low power consumption requirements are there in the circuits. This hybrid CMOS full adder uses a combination of PMOS and NMOS transistors to achieve low power consumption, high speed, and area efficiency. The sum and carry circuits are designed to implement the respective logical functions using a mix of pass transistor logic and traditional CMOS techniques. The resulting full adder is well-suited for embedded systems where power and speed are critical factors.