A SOT-MRAM-Based CIM Design With Multi-Bit Resistance-Sum Paradigm and Non-Idealities Tuning Mechanism

Computing-in-memory (CIM) technique has attracted considerable attention as a candidate path to surmount the “memory wall” bottleneck in the post-Moore era. Due to its non-volatile characteristics, low power dissipation, and short response latency, magnetoresistive random access memory (MRAM) has emerged as a widely researched memory medium for CIM designs. This article proposes a multi-bit CIM paradigm based on the resistance-sum principle. This paradigm is implemented in our fabricated dual-MTJ-single-bottom-electrode spin-orbit torque MRAM (SOT-MRAM), referred to as MB-SOT-CIM, which can also be conveniently configured for binary neural networks (BNNs). Thanks to this paradigm, over 50% weight loading is eliminated. Besides, a non-idealities tuning mechanism is presented for the time-domain output unit through a concise lookup table (LUT). This work is simulated using a 40-nm foundry process based on the test parameters of our fabricated SOT devices. Due to the utilization of higher-resistance SOT devices and optimal circuit design, the results demonstrate that the proposed MB-SOT-CIM achieves 57.35 TOPS/W energy efficiency under 4/4/4-bit precision, normalized to 917.6 TOPS/W at 1-bit precision, while exhibits enhanced robustness. This offers a promising technical solution for edge devices.