Investigation of Pocket Engineering in GNR Tunnel-FET Using Analog/RF Figures of Merit

This work investigates analog/RF performance characteristics of graphene nanoribbon (GNR) tunnel field-effect transistors (TFETs) featuring source-end pocket engineering. Utilizing self-consistent atomistic simulations and the nonequilibrium Green’s function (NEGF) framework, this novel research work focuses on optimizing pocket length for GNR TFETs by examining the on-current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text {on}}$ </tex-math></inline-formula>) to off-current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text {off}}$ </tex-math></inline-formula>) ratio <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text {on}}$ </tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {off}}$ </tex-math></inline-formula>, providing insights into digital performance parameters. The optimized pocket length identified for the observed device is 5 nm. Furthermore, to enhance performance in various analog and RF applications, the impact of pocket engineering on analog/RF figures of merit (FoM) are analyzed. Transconductance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g} _{m}$ </tex-math></inline-formula>), transconductance generation factor (TGF), output conductance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g} _{\text {ds}}$ </tex-math></inline-formula>), intrinsic gain (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g} _{m}{r}_{{0}}$ </tex-math></inline-formula>), gate capacitance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C} _{\text {G}}$ </tex-math></inline-formula>), cut-off frequency (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f} _{\text {T}}$ </tex-math></inline-formula>), and transconductance frequency product (TFP) are examined. The results indicate that GNR TFETs with pocket engineering perform better than conventional GNR TFETs. The improvements and the lags have been discussed in detail in this report.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2024-11-04
DOI
https://doi.org/10.1109/ted.2024.3484349
Citations
4
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
1.96
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article

Investigation of Pocket Engineering in GNR Tunnel-FET Using Analog/RF Figures of Merit

Md Akram Ahmad, Ashish Maurya, Jitendra Kumar
4 citations
IEEE Transactions on Electron Devices
VLSI and Analog Circuit Testing
1.96
article

Investigation of Pocket Engineering in GNR Tunnel-FET Using Analog/RF Figures of Merit

Md Akram Ahmad, Ashish Maurya, Jitendra Kumar
article en
4 citations

Abstract

This work investigates analog/RF performance characteristics of graphene nanoribbon (GNR) tunnel field-effect transistors (TFETs) featuring source-end pocket engineering. Utilizing self-consistent atomistic simulations and the nonequilibrium Green’s function (NEGF) framework, this novel research work focuses on optimizing pocket length for GNR TFETs by examining the on-current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text {on}}$ </tex-math></inline-formula>) to off-current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text {off}}$ </tex-math></inline-formula>) ratio <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text {on}}$ </tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {off}}$ </tex-math></inline-formula>, providing insights into digital performance parameters. The optimized pocket length identified for the observed device is 5 nm. Furthermore, to enhance performance in various analog and RF applications, the impact of pocket engineering on analog/RF figures of merit (FoM) are analyzed. Transconductance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g} _{m}$ </tex-math></inline-formula>), transconductance generation factor (TGF), output conductance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g} _{\text {ds}}$ </tex-math></inline-formula>), intrinsic gain (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g} _{m}{r}_{{0}}$ </tex-math></inline-formula>), gate capacitance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C} _{\text {G}}$ </tex-math></inline-formula>), cut-off frequency (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f} _{\text {T}}$ </tex-math></inline-formula>), and transconductance frequency product (TFP) are examined. The results indicate that GNR TFETs with pocket engineering perform better than conventional GNR TFETs. The improvements and the lags have been discussed in detail in this report.

IEEE Transactions on Electron DevicesVol. 71(12)
Presidency University (IN), Indian Institute of Technology Dhanbad (IN), Indian Institute of Technology Kanpur (IN)
Openalex Percentile: Top 12%
VLSI and Analog Circuit Testing
1.96
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