Optimized Leading Zero Count Structure for Arithmetic Computations

The Leading Zero Counting is an elementary block in floating point arithmetic operations. We present an optimized structure for Leading Zero Count (LZC) operations. Contingent on newly derived Boolean relations for the bits, 8-bit LZC is obtained. LZCs of further bit widths are designed and assessed. We focus on Application-Specific Integrated Circuits (ASIC) implementations of LZC at 45nm technology and thereby analyzed and compared the results with 3 other existing architectures. The results serve to have significant reductions in the overall power area delay product of the circuits.