Optimizing Spacer Width in N-Type Lateral Hetero-Structure Junctionless TFETs

In this article, to further the design of semiconductor devices, this work investigates the effects of spacer width modification on the functional features of junctionless tunnel field-effect transistors (JLTFETs). Comprehensive simulations and an examination of critical factors at spacer widths of 2, 3, and 4 nm were conducted using a 2-D Silvaco TCAD Simulator. After a thorough analysis, it has been observed that the spacer width had a strong effect on several number of device performance parameters, including the transconductance (g<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf>), drain current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf>), ratio of on/off current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>), threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>), and parasitic capacitances (C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</inf>, C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</inf>, and C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gg</inf>). Interestingly, 2 nm spacer width was the best value for RF performance, as seen by greater transconductance and decreased parasitic capacitance. Furthermore, unusual threshold voltage behavior was noted at 3 nm spacer width, which calls for more investigation. These results provide insightful information on JLTFET optimization for various electronic applications, directing future studies and development initiatives in the field of semiconductor device design.