Exploring Diverse Logic Implementations and Full Adder Circuit Designs

In the last few years scientists are more focused towards in the reduction of the chip size and on the low power consumption of the chips in VLSI design. In digital electronics there is a digital circuit called as full adder generally which is used in the addition of two bits in various devices. In this paper there is a review of various full adders by using different logic styles such as CMOS(Complementary Metal Oxide Semiconductor), CMOS Domino Logic, Emitter-Coupled Logic, Pass Transistor Logic and Transistor-Transistor Logic. It operates very fast and uses very little power. In this paper there is a comparative study of various Full-Adders by using different techniques to show the results for the technique which is better for carrying out of Full-Adder Circuit in digital electronics. Here in this all the full adders which is taken for the review are simulated on 45-nm of technology. The parameters which are compared here is Delay(pS), Power(uW) and PDP or Power Delay Product(aJ). In all the full adders which are discussed in this paper XOR and XNOR transistors are used. Here in this paper simulation results are also added which is of HPHFA full adder. Here in this paper it is observed that HPHFA full adder 10.3-40.5% and 10.7-45.9% is better in terms of delay and PDP.