<i>K</i>-Band Frequency Mixing Divider for Translation Loop Applications

A K-band frequency mixing divider scheme includes a downconverter double-balanced mixer and a divide-by-3 injection-locked frequency divider implemented with a TSMC 180-nm CMOS process is proposed in this letter. The compact structure is suitable for low-phase noise translation loop frequency synthesizers. Based on an inductive degeneration topology, the proposed mixer achieves a voltage conversion gain (CG) of 9.1 dB and a noise figure of 8.7 dB at 25 GHz radio frequency (RF) frequency. The measured locking range of the proposed circuit is from 8 to 8.5 GHz when the RF input signal varies from 21.5 to 25.5 GHz. The locking phase noise of injection frequency divider (ILFD) at a 100-kHz offset frequency was -117.4 dBc/Hz, while the injection signal had a phase noise of -108.3 dBc/Hz. The whole chip size, including the on-wafer pads, is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.2\times 0.986$ </tex-math></inline-formula> mm2.