Design of 8T DTMOS Schmitt Trigger SRAM Cell for IOT Applications

Abstract Internet of things (IoT) based systems require power-efficient circuits to raise the battery lifeline. This study presents a single-ended 8T SRAM cell. The core of the proposed 8T SRAM cell is composed of a Schmitt-Trigger circuit which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. Read operation of the proposed cell is conducted using the shared footer per word transistor. The write path is cut-off during the read operation, improving RSNM. A transmission gate placed in the cell core is used to cut the feedback path during write operation. To prove superiority of the proposed cell it is compared with four state-of-the-art SRAM cells under identical conditions on Cadence Virtuoso using 45nm technology at VDD=0.8 V. The proposed circuit shows a 135.74 % improvement in terms of RSNM and a 44.04 % improvement in terms of peak-to-peak power compared to the 6T DTMOS Cell.