Field Programmable Gate Array Implementation of Reversible Binary Coded Decimal Multiplier

Decimal data processing is gaining more importance in recent years, which increase the need for hardware support. The significance of reversible logic is growing in the research area of Very Large-Scale Integration (VLSI) design so as to minimize the power dissipation. This logic can be employed in the computing technologies like nanotechnology, quantum computing, digital signal processing, optical computing, low power Complementary Metal Oxide Semiconductor (CMOS), etc., Multiplier is one of the essential components in a processor. Hence so as to enhance the efficiency of the method, better multiplier architectures are used. This paper presents a new method of Binary Coded Decimal (BCD) multiplication using Reversible logic. Based on a two-stage operation procedure, this concept calls for a binary-to-BCD conversion step and a BCD multiplication stage. Here the first stage is implemented using Peres gate and the second stage is implemented using the combination of different reversible gates. The intended multiplier is constructed in a manner that the area, delay, power is reduced compared to the previous works in computing the BCD product and the implementation is carried out using Spartan 3A FPGA kit.