A Field-Programmable Gate Array-Based Quasi-Cyclic Low-Density Parity-Check Decoder with High Throughput and Excellent Decoding Performance for 5G New-Radio Standards

This work presents a novel fully parallel decoder architecture designed for high-throughput decoding of Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes within the context of 5G New-Radio (NR) communication. The design uses the layered Min-Sum (MS) algorithm and focuses on increasing throughput to meet the strict needs of enhanced Mobile BroadBand (eMBB) applications. We incorporated a Sub-Optimal Low-Latency (SOLL) technique to enhance the critical check node processing stage inherent to the MS algorithm. This technique efficiently computes the two minimum values, rendering the architecture well-suited for specific Ultra-Reliable Low-Latency Communication (URLLC) scenarios. We design the decoder to be reconfigurable, enabling efficient operation across all expansion factors. We rigorously validate the decoder’s effectiveness through meticulous bit-error-rate (BER) performance evaluations using Hardware Description Language (HDL) co-simulation. This co-simulation utilizes a well-established suite of tools encompassing MATLAB/Simulink for system modeling and Vivado, a prominent FPGA design suite, for hardware representation. With 380,737 Look-Up Tables (LUTs) and 32,898 registers, the decoder’s implementation on a Virtex-7 XC7VX980T FPGA platform by AMD/Xilinx shows good hardware utilization. The architecture attains a robust operating frequency of 304.5 MHz and a normalized throughput of 49.5 Gbps, marking a 36% enhancement compared to the state-of-the-art. This advancement propels decoding capabilities to meet the demands of high-speed data processing.