An Over 100% Fractional Bandwidth Low Noise Amplifier with Gate-Drain Transformer-Feedback in 90-nm CMOS Process

This paper presents a broadband low noise amplifier (LNA) operating from 13 to 40 GHz, designed for communication applications using TSMC 90-nm CMOS technology. To extend the bandwidth, the gate-drain transformer-feedback technique is employed at each stage. The proposed LNA achieves high gain and low noise figure simultaneously over a wide frequency range, while maintaining low power consumption. Measurement results demonstrate competitive performance, with a peak gain of 15.6 dB and a noise figure ranging from 2.3 to 4.8 dB across a 4-dB bandwidth spanning fro m 13.3 to 40.3 GHz. The DC power consumption of the design is only 11.7 mW, with an IP<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</inf> of -12 dBm and IIP<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> of -1.6 dBm at 28 GHz. Furthermore, the figure-of-merit (FoM) of this work is calculated to be 19.9 GHz/mW, showing its competitiveness among published Ku-band to Ka-band wideband LNAs. The entire chip occupies a compact area of 0.43 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, including pads.