A Low-Power 42 to 67 GHz Variable-Gain LNA in 22FDX® on Standard- and High-Resistivity Substrates with 3.4 dB Noise Figure

This paper describes the design and implementation of a 42-67 GHz LNA using GlobalFoundries’ 22 nm FD-SOI technology, that was fabricated on standard-resistivity as well as on high-resistivity substrate wafers. On the conventional standard-resistivity substrate, the proposed design achieves 3.8 dB of minimal noise-figure for a peak gain of 21.0 dB at its nominal bias under 13.7 mW of power-consumption. The LNA makes use of the unique back-gate bias node of the 22FDX® technology to offer 10 dB of gain-control over a 2 V bias range at the back-gates, and takes up an area of 0.17 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. On the high-resistivity silicon substrate, improvements of 0.9 dB in gain and 0.4 dB in noise-figure are achieved for this LNA, and these improvements are attributed to the increased quality factors of the integrated spiral inductors present in the design.

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Publication Details

Published
2024-09-23
DOI
https://doi.org/10.23919/eumic61603.2024.10732188
Citations
2
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.42
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article

A Low-Power 42 to 67 GHz Variable-Gain LNA in 22FDX® on Standard- and High-Resistivity Substrates with 3.4 dB Noise Figure

D. Bajon, Dimitri Lederer, Lucas Nyssens, Martin Rack et al.
2 citations
Radio Frequency Integrated Circuit Design
0.42
article

A Low-Power 42 to 67 GHz Variable-Gain LNA in 22FDX® on Standard- and High-Resistivity Substrates with 3.4 dB Noise Figure

D. Bajon, Dimitri Lederer, Lucas Nyssens, Martin Rack, J.‐P. Raskin, S. Wane
article en
2 citations

Abstract

This paper describes the design and implementation of a 42-67 GHz LNA using GlobalFoundries’ 22 nm FD-SOI technology, that was fabricated on standard-resistivity as well as on high-resistivity substrate wafers. On the conventional standard-resistivity substrate, the proposed design achieves 3.8 dB of minimal noise-figure for a peak gain of 21.0 dB at its nominal bias under 13.7 mW of power-consumption. The LNA makes use of the unique back-gate bias node of the 22FDX® technology to offer 10 dB of gain-control over a 2 V bias range at the back-gates, and takes up an area of 0.17 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. On the high-resistivity silicon substrate, improvements of 0.9 dB in gain and 0.4 dB in noise-figure are achieved for this LNA, and these improvements are attributed to the increased quality factors of the integrated spiral inductors present in the design.

DBV Technologies (France) (FR), UCLouvain (BE)
Affordable and clean energy
Openalex Percentile: Top 37%
Radio Frequency Integrated Circuit Design
0.42
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