6-12.5 GHz, 0.0076 mm², Low-Power PLL in 22 nm FDSOI for Multi Lane Applications

This work presents the design, implementation, and characterisation of a fully-integrated phase-locked loop in 22 nm FDSOI CMOS technology. The proposed PLL employs a feed-forward ring-based oscillator to achieve a compact footprint and wide tuning range. The proposed architecture is validated by designing a prototype that operates from 6 GHz to 12.5 GHz utilizing a 50 MHz reference. The power consumption at 12.5 GHz is 5.34 mW, and occupying only 0.0076 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. The measured phase noise at 12.5 GHz is -101.3 dBc/Hz, and the root-mean-square jitter is 306 fs. The achieved figure-of-merit is -288 dB.