A D-Band Mixer-First Receiver in 22-nm FD-SOI CMOS with Back-Gate Biasing for I/Q Imbalance Optimization

A D-band mixer-first receiver in CMOS 22-nm FDSOI with I/Q imbalance optimization is proposed in this paper. The optimization mechanism is implemented on I/Q mixers through adjusting back-gate voltages of the super-low threshold voltage (SLVT) transistors, resulting in a 36.1-dB image-rejection ratio (IRR) at 145 GHz. With a power consumption of 36.9 mW, the receiver achieves a conversion gain (CG) of 18.6 dB and a double-sideband (DSB) noise figure of 15.6 dB at 140 GHz. For zero-IF down-conversion, the proposed I/Q optimization shows EVM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</inf> improvement of 5.6 dB with a 16-QAM 500-MBd signal. Meanwhile for low-IF down-conversion, the receiver supports 64-QAM signal with a data rate of 7.2 Gb/s.