A Wideband Millimeter-wave Vector-Sum Phase shifter in 28-nm bulk CMOS

This paper presents a wideband vector-sum phase shifter (VSPS) operating within 21-43.9 GHz, implemented in TSMC 28-nm bulk CMOS. The VSPS comprises a quadrature all-pass filter (QAF) with a compensation network, a vector modulator with a compensation amplifier, and input and output wideband matching networks. Simulated phase and gain imbalances of the QAF are below 1.6° and 1 dB, respectively. Measured results of the proposed VSPS exhibit a peak gain of 1.8 dB (inclusive of input and output baluns), with a 3-dB bandwidth of 21-43.9 GHz and a DC power consumption of 38.7 mW. The measured RMS phase error and gain error are 0.75° to 1.25° and 0.57 dB to 1.35 dB, respectively. The core chip area is 0.34 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The circuit can cover mainstream communication frequency bands with a good performance, making it a promising candidate for practical applications.

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Publication Details

Published
2024-09-23
DOI
https://doi.org/10.23919/eumic61603.2024.10732387
Citations
1
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.21

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article

A Wideband Millimeter-wave Vector-Sum Phase shifter in 28-nm bulk CMOS

Hui‐Yang Li, Jin‐Xu Xu, Xiu Yin Zhang, Yifan Peng
1 citations
Radio Frequency Integrated Circuit Design
0.21
article

A Wideband Millimeter-wave Vector-Sum Phase shifter in 28-nm bulk CMOS

Hui‐Yang Li, Jin‐Xu Xu, Xiu Yin Zhang, Yifan Peng
article en
1 citations

Abstract

This paper presents a wideband vector-sum phase shifter (VSPS) operating within 21-43.9 GHz, implemented in TSMC 28-nm bulk CMOS. The VSPS comprises a quadrature all-pass filter (QAF) with a compensation network, a vector modulator with a compensation amplifier, and input and output wideband matching networks. Simulated phase and gain imbalances of the QAF are below 1.6° and 1 dB, respectively. Measured results of the proposed VSPS exhibit a peak gain of 1.8 dB (inclusive of input and output baluns), with a 3-dB bandwidth of 21-43.9 GHz and a DC power consumption of 38.7 mW. The measured RMS phase error and gain error are 0.75° to 1.25° and 0.57 dB to 1.35 dB, respectively. The core chip area is 0.34 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The circuit can cover mainstream communication frequency bands with a good performance, making it a promising candidate for practical applications.

South China University of Technology (CN)
National Natural Science Foundation of China, China Postdoctoral Science Foundation, Fundamental Research Funds for the Central Universities
Affordable and clean energy
Openalex Percentile: Top 47%
Radio Frequency Integrated Circuit Design
0.21
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