Ka-Band Cascode CMOS Power Amplifier with Improved Linearity Using Bias Optimization Technique

In this study, we presented a bias optimization design technique to maximize the linearity of the cascode power amplifier. Optimization was performed based on distortion and IMD3 analysis through continuous wave and two-tone power simulation. The proposed optimization design technique was validated through measurements with 64-quadrature amplitude modulation (QAM) signals, which had a 100-MHz channel bandwidth. The designed differential cascode power amplifier, using a 65-nm RF CMOS process, achieved an output 1-dB compression point (OP1dB) of 17.0-dBm, a saturation output power (PSAT) of 18.5-dBm, and a peak power-added efficiency (PAE) of 32.7% at 28 GHz. Furthermore, the 64-QAM performance achieved a PAVG of 11.7-dBm and a PAEAVG of 16% with —25 dB error vector magnitude (EVM) and the adjacent channel leakage ratio (ACLR) of —28.7 dBc. Through the bias optimization technique, PAVG and PAEAVG were improved by 1.1-dBm and 2.4%, respectively.