The Impact of Nanoscale CMOS Devices Scaling and Variations on mm-Wave CMOS Performance

The impact of nanoscale CMOS devices scaling and variations as well as layout dependent effects (LDE) on high frequency performance appears as the most critical challenge to nanoscale devices optimization and modeling for mm-Wave and Sub-THz CMOS circuits simulation and design. This paper presents an extraordinary finding in sub-60 nm devices which can exactly meet the foundry golden die target in terms of IDS and g<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> from DC measurement on different dies/lots but exhibit dramatic differences at the high frequency performance, such as f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> and f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf>. It highlights a fundamental problem with the foundry PDK (Process Design Kit) and compact models which are limited to I-V and C-V curves fitting and become invalid for high frequency simulation. For the first time, a high precision parameters extraction method and analytical models are developed based on high frequency characterization to precisely identify sub-nm or atomic scale variations in nanoscale device parameters and explain the mechanism responsible for very different impact on f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> and f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> in mm-Wave domain. This fully high frequency based method can facilitate accurate simulation and prediction of f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> and f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> subject to nanoscale devices scaling and variations.