A mm-Wave Two-Stage CMOS LNA Using Noise Cancelling and Post-Distortion Techniques

A wideband two-stage CMOS low-noise amplifier is proposed for millimeter-wave applications. For the first stage, a noise-canceling path is added in parallel with a main path for a low-noise target. The noise-cancelling condition of the main path is roughly maintained in amplitude by a proper gm ratio, and in phase by slightly shifting central frequency of an LC tank. By applying a post-distortion technique to the second stage, an auxiliary path is appended to tap and cancel distortions of the main path from its output side. Double-peak-coupling resonators bridge the stages for a wideband profile. Experimental results have shown 20 dB peak gain and minimal 3.1 dB NF across the passband of 28-37 GHz. Moreover, the inband third-order input intercept point (IIP3) is shown as -9.4~-2 dBm. Fabricated in a 65 nm CMOS process, the circuit core consumes 17.8 mW with a 1.2 V supply and occupies an area of 869×274 um<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.

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Publication Details

Published
2024-09-23
DOI
https://doi.org/10.23919/eumic61603.2024.10732461
Citations
7
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
1.46
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article

A mm-Wave Two-Stage CMOS LNA Using Noise Cancelling and Post-Distortion Techniques

Benqing Guo, Jun Chen
7 citations
Radio Frequency Integrated Circuit Design
1.46
article

A mm-Wave Two-Stage CMOS LNA Using Noise Cancelling and Post-Distortion Techniques

Benqing Guo, Jun Chen
article en
7 citations

Abstract

A wideband two-stage CMOS low-noise amplifier is proposed for millimeter-wave applications. For the first stage, a noise-canceling path is added in parallel with a main path for a low-noise target. The noise-cancelling condition of the main path is roughly maintained in amplitude by a proper gm ratio, and in phase by slightly shifting central frequency of an LC tank. By applying a post-distortion technique to the second stage, an auxiliary path is appended to tap and cancel distortions of the main path from its output side. Double-peak-coupling resonators bridge the stages for a wideband profile. Experimental results have shown 20 dB peak gain and minimal 3.1 dB NF across the passband of 28-37 GHz. Moreover, the inband third-order input intercept point (IIP3) is shown as -9.4~-2 dBm. Fabricated in a 65 nm CMOS process, the circuit core consumes 17.8 mW with a 1.2 V supply and occupies an area of 869×274 um<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.

Huawei Technologies (China) (CN), Chengdu University of Information Technology (CN)
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Openalex Percentile: Top 17%
Radio Frequency Integrated Circuit Design
1.46
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