Layout-Aware Equivalent Circuit Models for Accurate Deembedding and Simulation of mm-Wave CMOS Device Performance

New equivalent circuit models with layout dependent parameters have been developed for openM1 and shortM1 pads, and full structure with devices to realize accurate high frequency simulation before and after deembedding. The parasitic resistance, inductance, and capacitance (RLC) originated from the pads, transmission lines (TML), and lossy substrate will lead to a dramatic degradation of the current gain and power gain, and thus abnormally low f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> and f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> in nanoscale CMOS devices. A clean deembedding achieved by using openM1 and shortM1 to the bottom metal (M1) can achieve super-300 GHz f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> and f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> in multi-finger (MF) nMOSFETs with optimized layout aimed at mm-Wave CMOS circuit design. The developed models can accurately simulate the high frequency performance with the impact of parasitic RLC and layout dependent effects. Also, the equivalent circuits with scalable model parameters for finger numbers can be easily implemented for high frequency circuit simulation and design.