A Continuous-Time Sigma-Delta ADC for Chopped Sensors with Digital Only Demodulation

This paper presents a direct-to-digital architecture intended for chopped sensors and illustrated with a 3-bit <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2^{nd}$</tex> order continuous-time Sigma-Delta <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Sigma\Delta)$</tex> ADC. To avoid folding of the quantization noise, no “unchopping” stages are present inside the converter and a digital sinusoidal demodulation is introduced, resulting in a peak SNR of 55dB dominated by white noise. Analog offset ripple loops are circumvented, and complexity is moved into the digital domain to enable area reduction, especially for lower technology nodes.