Modeling Stress Effects from Fin Isolation in 7nm FinFET Transistors

This paper investigates the impact of stress, developed during FinFET device fabrication, on electrical characteristics in a 7nm node silicon VLSI technology, focusing on the effects of the active diffusion isolation. A 3D TCAD process model of a FinFET device was created and validated by measured data for the isolation with a Single Diffusion Break and a Double Diffusion Break. The model effectively calculates the stress distributions for PMOS and NMOS transistors under various isolation environments and predicts impacts on Fin FE T performance.