A Low Power Cascaded Eight-Channel D-Band Receiver using Single LO Mixer and On-Chip Feeder in 40-nm CMOS for Massive Array FMCW Radar

This paper introduces a 120 GHz low power four-channel receiver chip and cascaded antenna integrated eight-channel receiver module implemented in a 40nm CMOS process. On-chip antenna feeder and reference LO repeater are implemented to facilitate the antenna and multi-chip integration without complex and expensive packaging processes. The proposed receiver consists of high multiplying ratio (×32) frequency multiplier with reference LO repeater, a four-stage low noise amplifier (LNA), single LO mixer (SLM), transimpedance amplifier (TIA), and baseband amplifier (BBA). To demonstrate multichannel scalability, two receiver chips are cascaded using LO repeater to form an eight-channel receiver module, which is fully packaged with antennas. The over the air test of the eight-channel antenna integrated receiver module demonstrates a peak gain of 62.6 dB, while consuming 370 mW, 46.3 mW per each channel.