Systolic Array Matrix Multiplication Accelerator

Systolic arrays are a simple solution to accelerate matrix multiplication. Matrix multiplication is a common operation used in artificial intelligence. We designed a loosely-coupled matrix multiplier with a 2D systolic array. The accelerator is configured with matrices parameters. The host raises a start flag to start an operation and when is completed another flag is raised by the accelerator. The accelerator has dedicated memory interfaces. The accelerator was designed in Sytem Verilog. The design was synthesized targeting an AMD/Xilinx VCU128 FPGA to measure the area utilization for various 2D systolic array dimensions. Another tests counted the clock cycles for the matrix multiplication. To reduce the total operation time, we proposed a parallel data flow. The design works on different clock domains: for the interfaces and the internal logic. Our experimental results suggest that our accelerator is up to 3.1X faster for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> Systolic Array and up to 145.5X faster for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$64\times 64$</tex> Systolic Array compared to baseline RISC- V processor.