A 36 V Chopper Offset-Stabilized Operational Amplifier With Fast Settling and Reduced Input Transient Currents

The paper presents a dual mux-friendly high voltage chopper offset-stabilized operational amplifier with a symmetrical <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$RC$</tex> notch filter, having a 4–36 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V$</tex> supply range, and being fabricated in a 0.25 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu m$</tex> CMOS process. The chopper stage operates at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$300 kHz$</tex> New mux-friendly and settling-enhancing techniques are used, together with a modified input stage for delivering high Slew-Rate. The circuit has a typical offset voltage of 1. 5 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu V$</tex> a settling time of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.75\mu s$</tex>, a minimum Power Supply Rejection Ratio (PSRR) and Common Mode Rejection Ratio (CMRR) of 145 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$dB$</tex>, a noise Power Spectral Density <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(PSD)$</tex> of 7.5 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$nV/\surd {}Hz, 15 MH\mathrm{z}$</tex> unity gain bandwidth, and 20 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V/\mu s$</tex> Slew-Rate, while consuming 1. 75 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$mA$</tex> per channel.