BTI Tolerant Clock Tree Synthesis using LP-based Supply Voltage Alignment

Clock tree synthesis (CTS) has become a critical step in designing the high performance synchronous system. The clock gating technique is one of the well-known methods for reducing power consumption. However, it may cause bias temperature instability (BTI)-induced Vth degradation of clock buffers and asymmetric aging resulting in large clock skew. In this paper, we propose a novel symmetrical buffered clock tree synthesis with supply voltage alignment to handle BTI. As the first step, a symmetrical abstract tree topology with minimized power consumption is generated in bottom-up stage. Second, the top-down stage estimates asymmetric BTI caused by clock gating with signal probability. Prior to the placement step, the linear programming (LP)-based algorithm is applied to find optimal supply voltages to buffers at each tree level while satisfying clock skew constraints. Finally, wire routing is performed using wire snaking to complete the clock tree synthesis. Experimental results show that the proposed CTS achieves on average 51% reduction in clock skew compared to existing CTS methods.