A Reduced overhead Accumulator-based BIST scheme for Two-pattern generation

Two-pattern tests target the detection of common failure mechanisms in CMOS VLSI circuits, modelled as stuck-open or delay faults. In this paper, a Reduced-overhead Accumulator-Based BIST scheme for Two-pattern generation (RABIT) is presented, that generates an exhaustive n-bit two-pattern test. RABIT is implemented in hardware utilizing an accumulator whose inputs are driven by a binary counter. An important advantage of the presented scheme is that it can be implemented by augmenting existing data path components, rather than building a new pattern generation structure. Furthermore, with the proposed scheme, the requirement for additional (i.e. control and/or accompanying) circuitry is eliminated. Comparisons with previously proposed schemes reveal that the proposed here scheme presents lower hardware overhead for the implementation of the BIST structure.