Design of 3.5 GHz Cascode CMOS Class E Power Amplifier for 5G Application

The rapid growth of IoT and advancements in cellular technology have increased the demand for efficient data services, especially with 5G. The power amplifier (PA) is crucial in the RF front-end of transmitters, making its high efficiency vital for effective data transmission. This paper proposes a novel RF PA schematic designed to address these challenges by integrating a two-stage architecture comprising a driver stage and a power stage. The driver stage utilizes a capacitive feedback and pi-matching cascade Class AB topology with reverse body biasing to enhance power gain while minimizing power consumption. The power stage employs a cascade class E topology to achieve higher power added efficiency (PAE) is implemented using CMOS RF 0.18-μm technology. The output 1dB compression point (OP1dB) of 2.35 dBm and the saturated output power of 8.2 dBm were shown in the simulations of the suggested PA design, which showed a peak simulated PAE of 50.2% and resulting in an overall power gain of 23.4 dB. These results indicate that the proposed RF PA offers a highly efficient solution for 5G communication systems, effectively improving power amplifier performance without compromising critical parameters.