An Efficient Hardware Implementation of FPGA-Based Stereo Matching Using a Single Path SGM Direction

This paper focuses on the implementation of FPGA-based stereo matching with minimal hardware utilization, particularly for medium- to low-end FPGAs with limited hardware resources. Due to its ability to rapidly reconstruct the distance of an object from two stereo images, stereo matching has been widely employed in robot navigation, advanced driver assistance systems (ADAS) in automotive, and agricultural. To achieve minimal hardware requirements for stereo matching implementation, we offer stereo matching with a tiny window buffer for cost matching computation utilizing sum of absolute difference (SAD). Furthermore, a single path semi-global matching (SGM) direction is used to boost the smoothness and discontinuity of the disparity image. According to the experimental results obtained with the Xilinx Zynq-XC7Z020 using a 4x4-pixel window size and single path SGM, the amount of required FPGA resources are 9% FF, 18% LUT, 5% BRAM, and 136 MHz working frequency. For the execution time, it takes 1.68 seconds.