INVESTIGATION OF THE EFFECTIVENESS OF CACHE COMPRESSION IN CENTRAL PROCESSORS USING THE BASE-DELTA-IMMEDIATE
This paper presents a design in the SystemVerilog hardware description language implementing a system consisting of a cache memory of 32 KB, cache controller, main RAM, compressor and decompressor. The system uses its own implementation of the Base-Delta-Immediate compression algorithm with the logic of storing, reading and writing compressed data in the cache. The results are obtained in the form of cache hits and compression ratio.
Authors
- V.R. Polyakov
- M.R. Pastukhov
Institutions
- Volgograd State Technical University (RU)
Publication Details
- Published
- 2024-10-21
- DOI
- https://doi.org/10.61527/appfe-2024.70
- Primary Topic
- Parallel Computing and Optimization Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00