Design and Implementation of Image Acquisition and Signal Transmission Functions based on FPGA

Abstract In recent years, video network monitoring systems have evolved rapidly, from the first generation of digital-analogue systems to the fully IP-based systems. Based on the FPGA core, this design focuses on image acquisition and information transmission. The FPGA expansion board contains several peripheral modules, including the OV7670 camera captures images, DRAM stores data, and FIFO handles cross-clock domain signal transmission. While the reference clock is 40ns, in this system, the clock period is 20ns, making two clock cycles equal to one reference clock cycle. Then, two counters are used, one is the reference clock and another is the line synchronization (cnt1) to count 800 clock cycles per line. The end of a line is indicated by end_cnt0, and FIFO data is stored in SDRAM. Configuring the VGA display driver allows image data to be transmitted and displayed on the VGA screen. The system features a simple structure, high resource utilization, and strong reliability.