Power and area-efficient digital filters for communication applications

The paper introduces an innovative time-dependent finite impulse response (FIR) filter designed for utilization in time-mode signal processing systems like mobile phones and digital transmitters-receivers. The filter’s functioning structure is embedded in the principles of high-level transformation techniques like parallel processing and folding. In this paper 6-tap FIR filter is designed and implemented using parallel processing and folding techniques for low power consumption and area minimization. The proposed FIR filter is modeled in Xilinx using Verilog hardware descriptive language and synthesized with the XST tool. The target implementation platform is the Xilinx ML605 embedded development kit to investigate the LUTs and power consumption of the design. The proposed filter reduces the major concern parameters of a design as power and area. The implementation results discover that the area is reduced to 90.83% of the existing method and power is reduced to 67.25% of the existing method. The findings represent a significant step ahead in hardware efficiency optimization.