Training-Free Parameter Extraction for Compact Device Models Using Sequential Bayesian Optimization With Adaptive Sampling

This work presents a computationally efficient approach for extracting compact model parameters with minimal training requirements. Bayesian optimization (BO) is employed in multiple stages to predict the optimum compact model parameters. Initially, the methodology is applied to the MIT virtual source model (MVS 2.0) for extremely thin silicon-on-insulator (ETSOI) devices, nanosheet FETs (NsFETs), and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {MoS}_{{2}}$ </tex-math></inline-formula>-based 2-D material-based FETs (2DFETs). Subsequently, it is demonstrated on the Berkeley short-channel IGFET model (BSIM) common multigate (CMG) compact model for NsFETs. Through sequential processing, adaptive sampling, successive domain reduction, and fine-tuned objective functions, the framework achieves precise and efficient fitting of both global and local model parameters across a range of devices, all in a reduced number of iterations, irrespective of the compact model used.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2024-10-25
DOI
https://doi.org/10.1109/ted.2024.3478177
Citations
4
Primary Topic
Advancements in Photolithography Techniques
Type
article
Field-Weighted Citation Impact
0.83
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article

Training-Free Parameter Extraction for Compact Device Models Using Sequential Bayesian Optimization With Adaptive Sampling

Om Maheshwari, Nihar R. Mohapatra, Aishwarya Singh
4 citations
IEEE Transactions on Electron Devices
Advancements in Photolithography Techniques
0.83
article

Training-Free Parameter Extraction for Compact Device Models Using Sequential Bayesian Optimization With Adaptive Sampling

Om Maheshwari, Nihar R. Mohapatra, Aishwarya Singh
article en
4 citations

Abstract

This work presents a computationally efficient approach for extracting compact model parameters with minimal training requirements. Bayesian optimization (BO) is employed in multiple stages to predict the optimum compact model parameters. Initially, the methodology is applied to the MIT virtual source model (MVS 2.0) for extremely thin silicon-on-insulator (ETSOI) devices, nanosheet FETs (NsFETs), and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {MoS}_{{2}}$ </tex-math></inline-formula>-based 2-D material-based FETs (2DFETs). Subsequently, it is demonstrated on the Berkeley short-channel IGFET model (BSIM) common multigate (CMG) compact model for NsFETs. Through sequential processing, adaptive sampling, successive domain reduction, and fine-tuned objective functions, the framework achieves precise and efficient fitting of both global and local model parameters across a range of devices, all in a reduced number of iterations, irrespective of the compact model used.

IEEE Transactions on Electron DevicesVol. 71(12)
Indian Institute of Technology Gandhinagar (IN)
Openalex Percentile: Top 26%
Advancements in Photolithography Techniques
0.83
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Training-Free Parameter Extraction for Compact Device Models Using Sequential Bayesian Optimization With Adaptive Sampling — Om Maheshwari, Nihar R. Mohapatra, et al. · IEEE Transactions on Electron Devices (2024) | TGRS Research Map | TGRS