Open-Source Internal Signal Analysis Unit for FPGA Paired With Rust Real-Time Monitor GUI

To address the gap in the tooling software for verifying Field Programmable Gate Array (FPGA) design, this paper introduces a Verilog implementation of a fully synthesizable unit for monitoring values of internal wires and registers. The unit samples an arbitrary number of internal signals and packages them into a Universal Asynchronous Receiver Transmitter (UART) message. Even when analysing multiple bit values only three FPGA board pins are required to transmit and receive messages using UART, in contrast to the conventional hardware logic analyzers where numerous pins are needed. The message is then sent from the FPGA to the Real-Time Monitor (RTM) application running on a host PC. Developed using the Rust programming language, the application ensures reliability, performance, memory safety, and efficiency. The resource utilization of the unit, deployed on the Gowin GW1NR-9 27 MHz chip, is presented. The unit, along with the RTM application, can be efficiently utilized for verifying arbitrary Verilog designs or employing them as an acquisition or monitoring hardware-software product.