Optimized Bus-Clamping Modulation Strategies for Dual-Inverter Topology
The Dual-Inverter (DI) emerges as a viable solution to address the ever-growing demands of electric drives, encompassing fault tolerance capability, waveform quality, superior DC-bus voltage utilization, and multilevel operation. The DI with isolated DC sources eliminates the path for zero sequence current (ZSC), thereby enabling the implementation of various modulation strategies. This paper introduces two bus-clamping modulation strategies aimed at minimizing switching losses for DI with isolated DC sources. The effectiveness of these modulation strategies is validated using a DI model in the MATLAB/Simulink environment, incorporating SiC MOS-FETs transistors parameterized in accordance with the manufacturer’s datasheet. An induction machine with a rated power of 12 kW serves as the load for DI.
Authors
- Filip Baum (ORCID: https://orcid.org/0000-0003-0876-8893)
- Jan Bauer (ORCID: https://orcid.org/0000-0002-0657-1213)
- Ondrej Lipcak (ORCID: https://orcid.org/0000-0001-6769-5714)
- Jakub Kucera (ORCID: https://orcid.org/0009-0003-1978-0377)
- Petr Zakopal (ORCID: https://orcid.org/0009-0000-9334-3659)
Institutions
- Czech Technical University in Prague (CZ)
Publication Details
- Published
- 2024-09-30
- DOI
- https://doi.org/10.1109/pemc61721.2024.10726324
- Primary Topic
- Multilevel Inverters and Converters
- Type
- article
- Field-Weighted Citation Impact
- 0.00