A Digital Thermistor Read-Out Based on Charge-Discharge Topologies Coupled With Optimal Linearization Strategies

This article proposes a simple and low-component count linearizing digitizer for thermistor interfacing. The proposed digitizer employs a simple charge-discharge (C-D) thermistor interface that selectively charges and discharges a capacitor between two voltage thresholds. This circuit aids in the thermistor linearization, requiring just two conversion cycles (as opposed to five in prior-art) for its operation. The article first presents a single-mode linearizing digitizer whose nonlinearity is minimized using the optimal choice of a resistance value. This is followed by the discussion of a multimode hybrid digitizing approach and associated new linearization function (with nonlinearity minimized using the optimal choice of a resistance value and software-implemented parameters). The differential evolution (DE) algorithm is employed for optimization, wherein important practical constraints are considered. The potential error sources are analyzed and quantified. Further, the performance analysis of the proposed schemes is performed using simulation and hardware-based experimental studies. The results demonstrate the ability of the developed schemes to render linear digital output characteristics when interfacing with typical thermistor operating over different temperature spans. The maximum nonlinearity of the developed hybrid-based digitizer observed during experimentation is 0.42% for 5 to 45 and 1.28% for 0 to 120. A detailed comparison of the proposed digitizer with contemporary thermistor linearizers is also reported in this article.