An online method for identifying metering relative errors in wide‐area interconnection CVTs using PMU measurements, SDP graphs, and ResNet50‐L1M

Abstract This paper proposes an online identification method utilizing phasor measurement unit (PMU) measurements, symmetric dot pattern (SDP) graphs, and the ResNet50‐L1 M model to facilitate the rapid identification of metering relative errors among interconnected capacitor voltage transformers (CVTs) in wide‐area substations within power systems. First, PMUs measured the three‐phase voltage data from interconnected CVTs across wide‐area substations. The amplitude differences of the three‐phase voltages were converted into Euclidean distances, which were then transformed into SDP graphs, with each type of metering relative error corresponding to a distinct SDP graph. The ResNet50‐L1 M model was established by integrating an L1 norm‐based attention mechanism into the ResNet50 architecture. This model was then trained on CVT SDP graphs representing various error states to develop an online error identification system. The effectiveness of the proposed method was evaluated based on data from the “Houshou transmission line” in Ningxia province, which connects the 330 kV Niushoushan substation and the 330 kV Houqiao substation operated by the State Grid Corporation of China. With 16 different error states tested, the model achieved an identification accuracy rate of 89.39%, demonstrating a notable improvement over other methods in comparative tests.

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Publication Details

Journal
IET Science Measurement & Technology
Published
2024-10-23
DOI
https://doi.org/10.1049/smt2.12225
Citations
2
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
Field-Weighted Citation Impact
0.42

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article

An online method for identifying metering relative errors in wide‐area interconnection CVTs using PMU measurements, SDP graphs, and ResNet50‐L1M

Chunyang Jiang, Feng Zhou, Xiaodong Yin, Bolun Du et al.
2 citations
IET Science Measurement & Technology
Integrated Circuits and Semiconductor Failure Analysis
0.42
article

An online method for identifying metering relative errors in wide‐area interconnection CVTs using PMU measurements, SDP graphs, and ResNet50‐L1M

Chunyang Jiang, Feng Zhou, Xiaodong Yin, Bolun Du, Shengguo Xia
article en
2 citations

Abstract

Abstract This paper proposes an online identification method utilizing phasor measurement unit (PMU) measurements, symmetric dot pattern (SDP) graphs, and the ResNet50‐L1 M model to facilitate the rapid identification of metering relative errors among interconnected capacitor voltage transformers (CVTs) in wide‐area substations within power systems. First, PMUs measured the three‐phase voltage data from interconnected CVTs across wide‐area substations. The amplitude differences of the three‐phase voltages were converted into Euclidean distances, which were then transformed into SDP graphs, with each type of metering relative error corresponding to a distinct SDP graph. The ResNet50‐L1 M model was established by integrating an L1 norm‐based attention mechanism into the ResNet50 architecture. This model was then trained on CVT SDP graphs representing various error states to develop an online error identification system. The effectiveness of the proposed method was evaluated based on data from the “Houshou transmission line” in Ningxia province, which connects the 330 kV Niushoushan substation and the 330 kV Houqiao substation operated by the State Grid Corporation of China. With 16 different error states tested, the model achieved an identification accuracy rate of 89.39%, demonstrating a notable improvement over other methods in comparative tests.

IET Science Measurement & TechnologyVol. 19(1)
Guizhou Electric Power Design and Research Institute (CN), China Electric Power Research Institute, Huazhong University of Science and Technology (CN)
Electric Power Research Institute, China Electric Power Research Institute, National Key Research and Development Program of China, Science and Technology Project of State Grid
Openalex Percentile: Top 37%
Integrated Circuits and Semiconductor Failure Analysis
0.42
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