A FinFET-based static memory cell optimized for stability and low power consumption

Abstract As the semiconductor industry continues to push the boundaries of miniaturization, traditional MOSFET transistors are no longer the ideal choice for VLSI circuit design, particularly for memory cells where stability and power efficiency are critical. FinFET transistors, with their superior performance in mitigating process variations, enhancing gate control, and reducing leakage currents, offer a promising alternative. This paper presents a novel 9 T SRAM cell, carefully designed and simulated using 10 nm FinFET devices at a supply voltage of 0.55 V. The proposed cell achieves significant improvements in read stability (writability) through the implementation of read path isolation and feedback-cutting techniques, resulting in a minimum enhancement of 1.10 (1.19) times. Furthermore, the cell significantly reduces read, write, and leakage power by at least 7.03%, 8.66%, and 14.14%, respectively. These power reductions are attributed to the adoption of a single-bitline structure, transistor stacking in access paths, and the minimization of control signal activation. To ensure robust operation in real-world scenarios, the cell’s resilience to process variation is meticulously examined. Analysis reveals lower variability in both read stability and writability design metrics, demonstrating the cell’s inherent robustness to manufacturing imperfections.