Design and Implementation of True Random Number Test Pattern Generator for Enhanced BIST Performance in Integrated Circuits

Background: Built-In Self-Test (BIST) modules are crucial for integrated circuits (IC), providing automatic error detection and correction for memory and stuck-at faults. Traditional approaches, particularly Linear Feedback Shift Registers (LFSRs), have been limited by insufficient randomization and inefficient hardware resource utilization. Methods: This study addresses these limitations by developing True Random Number Test Pattern Generator (TRN-TPG) frameworks. The approach involves replacing conventional ring oscillators with Digital Clock Managers (DCMs) to enhance the tunability of phase and frequency of random numbers. Beat frequency detection is achieved using D-flip flops (D-FFs), post-processing units, and counters. Results: Simulation results demonstrate that the proposed TRN-TPG framework significantly improves performance compared to traditional methods. Specifically, it offers less utilization in terms of 16 number of look-up-tables, 0.54ns of latency, and 32.83mw of power consumption. Concluding Remarks: The findings suggest that the TRN-TPG framework is a superior alternative to conventional BIST designs, providing better randomization with lower hardware resource utilization.