An Efficient BCD Adder Design Utilizing Reversible Logic Techniques

Reversible logic gates are pivotal components in digital circuit design, embodying the principle of reversibility that ensures each input state maps uniquely to a distinct output state without loss of information. Leveraging these principles, this paper presents a novel design and validation of a Binary-Coded Decimal (BCD) adder utilizing reversible logic gates, specifically ASK gates and New Gate (NG). Through the seamless integration of ASK and NG gates, the proposed design achieves significant improvements in efficiency and performance metrics. The design and validation processes are carried out using Xilinx Vivado 2022.2 software. Notably, it demonstrates a substantial reduction in gate count and ancilla inputs while effectively managing garbage outputs. The design features a gate count of 11, employs 13 ancilla inputs, and generates 22 garbage outputs, showcasing a remarkable 63.33% reduction in gate count compared to existing architectures. These findings highlight the efficiency, scalability, and potential applications of the proposed design in various domains including quantum computing, low-power systems, error-correction mechanisms, cryptography.