Design and UVM based Verification of UART, SPI, and I²C Protocols

There are several hardware communication protocols available today, but the three most prevalent and frequently used are UART (Universal Asynchronous Receiver Transmitter), SPI (Serial Peripheral Interface), and $\mathbf{I}^{\mathbf{2}} \mathbf{C}$ (Inter-Integrated Circuit). This article discusses the working, implementation and verification of these protocols. It aims to highlight the difference in hardware requirements for implementation of each of these designs, and the difference in the approach of verification of these designs. The implementation of the design is done using Quartus Prime tool. An FSM is designed for each of these protocols which is then used to write the Verilog code for the design. The design is then synthesized for Cyclone V SE Base FPGA board. The resource utilisation for each protocol is discussed based on Combinational ALUTs and Dedicated Logic Registers used. UVM (Universal Verification Methodology) based verification is preformed for each of the design. A verification environment is developed using UVM. These environments were then compiled in QuestaSim 10.7c. UVM sequences are used to create the stimuli. The verification for each protocol differs in term of the sequences that are applied. UART verification proves to be a lot more challenging because of different parameters that are configurable, such as setting the baud rate, data length, stop bits and parity types. While SPI and $I^{2} \mathbf{C}$ have a similar type of sequences which are used for their verification, these are read, write, reset, and error sequences. However, upon implementation it can be seen that $I^{2} \mathbf{C}$ proves to be more resource efficient.