A Comparator Tree Design with Optimized Quantum Cost Using Reversible Logic Techniques

Reversible logic is gaining increasing significance in diverse research areas, including quantum computing, nanotechnology, and optical computing. The exploration of reversible gates has emerged as a cutting-edge research area, driving a wave of innovative developments aimed at maximizing resource efficiency. This work focused on creating highly efficient 2-bit, 8-bit, and 64-bit comparators, leveraging the advantages of reversible logic gates. The results obtained from the comparative analysis demonstrate substantial improvements in energy efficiency and computational speed compared to other architectures. The proposed design demonstrated superior performance with reduced quantum cost and delay while minimizing garbage outputs. Specifically, the quantum costs of the 2-bit, 8-bit, and 64-bit comparators were measured to be 20, 128, and 1136, respectively. These outcomes suggest substantial enhancements in a variety of parameters, which ultimately will result in a more efficient and effective design. The functionality of the designed comparator tree was validated using Xilinx Vivado 2022.2 and implemented in Verilog HDL.