Performance Analysis of Vedic Multiplier using Different Adders

In this paper, we present a comprehensive analysis of the performance of a Vedic multiplier utilizing various types of adders. The Vedic multiplier, inspired by ancient Indian mathematics, offers potential advantages in terms of speed and area efficiency compared to conventional multipliers. We explore the impact of different types of adders, such as ripple-carry adder, carry-look-ahead adder, carry-increament adder, carryskip adder and, carry-select adder on the overall performance of the Vedic multiplier. Our analysis involves simulation studies using modelsim and synthesis using xlinix 14.7 to evaluate critical metrics such as pin-to-pin delay, power consumption, total delay and area utilization. Through detailed experimentation and analysis, we aim to provide insights into the optimal configuration of adders for achieving enhanced performance in Vedic multiplier implementations. This research contributes to the understanding of efficient arithmetic unit design methodologies, with potential applications in high-speed digital signal processing, scientific computing, and other computation-intensive domains.